1. Field of the Invention
The present invention relates to an internal voltage generating circuit and a semiconductor integrated circuit device using the same, and particularly to an internal voltage generating circuit, which can precisely produce an internal voltage stably having a desired temperature characteristic even with a low power supply voltage, and a semiconductor integrated circuit device, in which the internal voltage generating circuit can be arranged with high area utilizing efficiency for stable transmission of to various elements on a chip.
2. Description of the Background Art
Owing to development of a semiconductor miniaturization technology in recent years, elements have been miniaturized to a higher extent, and high-density integration can now be achieved. The high-density integration has actualized an integrated circuit device, which includes a plurality of function circuits formed on a single chip to form one system, and is referred to as a System On Chip (SOC) or a system LSI (Large Scale Integrated circuit). Among various uses, mobile communication terminal devices, movie processing and communication networks strongly require such system LSIs, and these uses require high operation frequencies and low power consumption. In these uses, it is necessary to employ a power supply, which allows increase in current consumption due to a fast operation, to lower a leak current (off-leak current) flowing through a MOS transistor (insulated gate field-effect transistor) in an off state, and to lower current consumption, e.g., by lowering a power supply voltage.
For example, when an eDRAM (embedded Dynamic Random Access Memory), which is a kind of mixed-type memory arranged together with a logic such as a processor on a single chip, is used for conventional image processing, image data is transferred in a sequential fashion. Therefore, it is required only to increase operation speeds of column-related circuits, which are provided in connection with selection of the memory cell column, and current consumption is relatively small even in a fast operation. In the movie image processing, communication network or the like, data are often accessed in a random fashion, and for the fast operation in this random access, row-related circuits selecting the memory cell rows must operate fast so that the current consumption increases in the fast operation. For the above uses, it is required, in addition to stable supply of an operation current, to suppress the current consumption to the extent possible, e.g., by lowering the off-leak current and employing the low power supply voltage. For satisfying the above requirements, it is necessary to provide an internal voltage generating circuit, which can operate with a high operation frequency, and can stably supply an internal voltage and an internal power supply voltage with high precision even with a low power supply voltage.
For example, in a conventional system-on-chip having a memory and a logic arranged on the same semiconductor chip in a mixed fashion, a power supply circuit is arranged for each of a memory core circuit and a logic core circuit. In the memory core circuit, it is necessary, e.g., for a DRAM, to employ a constant voltage generating circuit, which precisely generates a constant voltage to be used for producing a sense amplifier power supply voltage for detecting a memory cell data, a circuit generating a negative voltage to be applied as a bias voltage to a back gate of a memory cell transistor, a circuit generating a boosted voltage to be transmitted to a word line, and a circuit generating a divided voltage for precharging bit lines during a standby state. In the logic core circuit, it may be necessary for suppressing off-leak current components of transistors to employ a circuit supplying a back gate bias voltage of the transistor as well as a circuit maintaining a negative voltage on a gate of the transistor in the off state. For generating these voltages, it is necessary to employ a circuit generating a reference voltage used as a reference for all voltages as well as a circuit generating a constant current.
However, if the power supply voltage is lowered for reducing the power consumption, these reference voltage generating circuit and constant current generating circuit operate in circuit operation regions close to threshold voltages of transistors, and it becomes difficult to operate stably the MOS transistors and to adjust circuit operation characteristics. In particular, for adjusting the temperature characteristics, a plurality of elements for compensating temperature characteristics are connected in series within a circuit, and a relatively large voltage difference is required for selectively setting these elements to active;/inactive states. Therefore, it becomes difficult to adjust sufficiently the temperature characteristics with a low power supply voltage.
A structure for accurately setting a negative voltage is disclosed in Japanese Patent Laying-Open No. 10-239357. In Japanese Patent Laying-Open No. 10-239357, a reference voltage having small temperature dependence is produced, and a MOS transistor is resistance-connected in series between an MOS transistor receiving on its gate the reference voltage and a negative voltage. Also, a reference transistor having a gate receiving the reference voltage and a source connected to a ground node is employed, and a current mirror supplies a current to the reference transistor as well as the above resistance-connected MOS transistor. By utilizing the fact that same gate-source voltage difference occurs in the resistance-connected MOS transistor and the series MOS transistor receiving the reference voltage on the gate, it is intended to detect a level of a negative voltage, which is an integral multiple of reference voltage Vref.
Japanese Patent Laying-Open No. 2003-168290 has disclosed an internal voltage down converter circuit, which stably produces an internal voltage even with a low power supply voltage. In a structure disclosed in this Japanese Patent Laying-Open No. 2003-168290, two differential stages formed of NMOS transistors are arranged in parallel, and two comparators thereof compare an internal power supply voltage with reference voltages at different voltage levels, respectively. According to the output signals of these comparator circuits, electric charges are supplied to or pulled out from an internal voltage line. By employing the differential stages formed of the NMOS transistors, it is intended to perform stably a differential amplifying operation even with a low power supply voltage.
A Japanese Patent Laying-Open No. 2000-353785 has disclosed a structure, which is intended to transmit stably an internal voltage to each of circuits in a memory chip over long distances. In the structure disclosed in Japanese Patent Laying-Open No. 2000-353785, the internal voltage transmission lines are surrounded by shield interconnections, which are fixed to a ground voltage and are arranged on the laterally opposite sides thereof and in upper and lower layers thereof.
In the structure disclosed in Japanese Patent Laying-Open No. 10-239357, the level of the negative voltage is detected by utilizing a reference voltage having small temperature dependence. However, no consideration is given to a manner of adjusting temperature characteristics of this reference voltage as well as a manner of stably producing the reference voltage with a low power supply voltage.
In the structure disclosed in Japanese Patent Laying-Open No. 2003-168290, comparing circuits of a current mirror type operate to adjust the level of the internal stepped-down voltage even with a low power supply voltage. Although the above operation is based on the premise that the reference voltage applied to the comparing circuit is produced based on a reference voltage independent of a temperature, no consideration is given to a manner of producing the reference voltage not having the temperature dependence.
Although Japanese Patent Laying-Open No. 2000-353785 has disclosed a structure, in which shield interconnections surround the internal voltage transmission lines in one memory chip, no consideration is given to an arrangement of a power supply circuit in a system LSI or the like having a plurality of core circuits therein.